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CY28405
CK409-Compliant Clock Synthesizer
Features
* Supports Intel Springdale/Prescott (CK409) * Selectable CPU frequencies * 3.3V power supply * Nine copies of PCI clock * Four copies 3V66 clock with one optional VCH * Two copies 48 MHz USB clock * Two copies REF clock CPU x3 3V66 x4 PCI x9 REF x2 48M x2 * Three differential CPU clock pairs * Dial-A-Frequency(R) * Supports SMBus/I2C Byte, Word, and Block Read/Write * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 48-pin SSOP package
Block Diagram
Pin Configuration
**FS_A/REF_0 **FS_B/REF_1 VDD_REF VDD_REF REF[0:1] XIN XOUT VDD_CPU VSS_REF CPUT[0:1,ITP], CPUC[0:1,ITP] *FS_C/PCIF0 *FS_D/PCIF1 *FS_E/PCIF2 VDD_PCI VSS_PCI PCI0 PCI1 VDD_3V66 3V66_[0:2] PCI2 PCI3 VDD_PCI VDD_PCI PCIF[0:2] VSS_PCI PCI[0:5] PCI4 PCI5 RESET#/PD# DOT_48 3V66_3/VCH USB_48 VSS_48 VDD_48MHz VDD_48 DOT_48
USB_48
XIN XOUT
XTAL OSC PLL 1
PLL Ref Freq
Divider Network
FS_[A:E] VTT_PWRGD# IREF
SELVCH
PLL2
2
MODE
PD#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDA VSSA IREF CPUT_ITP CPUC_ITP VSS_CPU CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS DNC*** DNC*** VDD VTT_PWRGD# SDATA SCLK 3V66_0 3V66_1 VSS_3V66 VDD_3V66 3V66_2/MODE* 3V66_3/VCH/SELVCH**
~
SSOP-48
* 150k Internal Pull-up ** 150k Internal Pull-down *** Do Not Connect
CY28405
SDATA SCLK
I2C Logic
WD Timer
RESET#
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 18
www.SpectraLinear.com
CY28405
Pin Description
Pin No. 1, 2 REF(0:1) Name Type O, SE I I Description Reference Clock. 3.3V 14.318-MHz clock output. 3.3V LVTTL latched input for CPU frequency selection. Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection. Connection for an external 14.318-MHz crystal output. CPU Clock Output. Differential CPU clock outputs. CPU Clock Output. Differential CPU clock outputs. Do Not Connect. O, SE I/O, SE PD I/O, SE PU 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. 48- or 66-MHz Clock Output. 3.3V selectable through external SELVCH strapping resistor and SMBus to be 66-MHz or 48-MHz. Default is 66-MHz. 0 = 66 MHz, 1 = 48 MHz 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. Reset or Power-down Mode Select. Selects between RESET# output or PWRDWN# input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD#, 1 = RESET Free Running PCI Output. 33-MHz clocks divided down from 3V66. PCI Clock Output. 33-MHz clocks divided down from 3V66. Fixed 48-MHz clock output. Fixed 48-MHz clock output. Current Reference. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for Power-down# active LOW. Watchdog Timeout Reset Output 3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E] input (active LOW). SMBus compatible SDATA. SMBus compatible SCLOCK. 3.3V Power supply for PLL. Ground for PLL. 3.3V Power supply for outputs.
1, 2, 7, 8, 9 FS_A, FS_B, FS_C, FS_D, FS_E 4 XIN
5 39, 42, 45 38, 41, 44 36, 35 30, 29 25
XOUT CPUT(0:1,ITP) CPUC(0:1,ITP) DNC 3V66(0:1) 3V66_3/VCH/SELVCH
O, SE O, DIF O, DIF
26
3V66_2/MODE
7, 8, 9
PCIF(0:2)
O, SE O, SE O, SE O, SE I I/O, PU I I/O I PWR GND PWR
12, 13, 14, PCI(0:5) 15, 18, 19 22 21 46 20 33 32 31 48 47 USB_48 DOT_48 IREF RESET#/PD# VTT_PWRGD# SDATA SCLK VDDA VSSA
3, 10, 16, VDD(REF,PCI,48,3V66,C 24, 27, 34, PU,ITP) 40 6, 11, 17, VSS(REF,PCI,48,3V66, 23, 28, 37, CPU,ITP) 43
GND
Ground for outputs.
Rev 1.0, November 20, 2006
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CY28405
MODE Select
The hardware strapping MODE input pin can be used to select the functionality of the RESET#/PD# pin. The default (internal pull up) configuration is for this pin to function as a RESET# Watchdog output. When pulled LOW during device power-up, the RESET#/PD# pin will be configured to function as a Power Down input pin.
Frequency Select Pins
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A through FS_E inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A through FS_E input values. For all logic levels of FS_A through FS_E, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD# and FS_A through FS_E transitions will be ignored.
Table 1. Frequency Selection Table Input Conditions FS_E FSEL_4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS_D FSEL_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS_C FSEL_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS_B FSEL_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS_A FSEL_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 100.7 100.2 108.0 101.2 Reserved Reserved Reserved Reserved 125.7 130.3 133.6 134.2 134.5 148.0 Reserved Reserved Reserved Reserved 167.4 170.0 175.0 180.0 185.0 190.0 100.9 133.9 200.9 Reserved 100.0 133.3 200.0 Reserved 3V66 67.1 66.8 72.0 67.5 Reserved Reserved Reserved Reserved 62.9 65.1 66.8 67.1 67.3 74.0 Reserved Reserved Reserved Reserved 55.8 56.7 58.3 60.0 61.7 63.3 67.3 67.0 67.0 Reserved 66.7 66.7 66.7 Reserved PCI 33.6 33.4 36.0 33.7 Reserved Reserved Reserved Reserved 31.4 32.6 33.4 33.6 33.6 37.0 Reserved Reserved Reserved Reserved 27.9 28.3 29.2 30.0 30.8 31.7 33.6 33.5 33.5 Reserved 33.3 33.3 33.3 Reserved VCO Freq. 805.6 801.6 864.0 809.6 Reserved Reserved Reserved Reserved 754.2 781.6 801.6 805.2 807.0 888.0 Reserved Reserved Reserved Reserved 669.6 680.0 700.0 720.0 740.0 760.0 807.2 803.4 803.6 Reserved 800.0 800.0 800.0 Reserved Output Frequency PLL Gear Constants (G) 24004009.32 24004009.32 24004009.32 24004009.32 Reserved Reserved Reserved Reserved 32005345.76 32005345.76 32005345.76 32005345.76 32005345.76 32005345.76 Reserved Reserved Reserved Reserved 48008018.65 48008018.65 48008018.65 48008018.65 48008018.65 48008018.65 24004009.32 32005345.76 48008018.65 Reserved 24004009.32 32005345.76 48008018.65 Reserved
Rev 1.0, November 20, 2006
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CY28405
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. The interface can also be accessed during power-down operation.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write and Block Read operation from any external I2C controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The Block Write and Block Read protocol is outlined in Table 3 while Table 4 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition Bit 7 (6:0) 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be `0000000' Description
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
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CY28405
Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Byte 0: Control Register 0 Bit 7 6 @Pup 0 1 Test Bit 3 PCIF PCI Reserved FS_E FS_D FS_C FS_B FS_A Name Description I2C_BYPASS_EN Reserved, Set= 0 IO PLL TEST PCI Drive Strength Override 0 = Force All PCI and PCIF Outputs to Low Drive Strength 1= Force All PCI and PCIF Outputs to High Drive Strength Reserved, Set= 0 PLL CPU VCO process correction test bit Power up latched value of FS_E pin Power up latched value of FS_D pin Power up latched value of FS_C pin Power up latched value of FS_B pin Power up latched value of FS_A pin
5 4 3 2 1 0
0 HW HW HW HW HW
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved CPUT_ITP, CPUC_ITP CPUT1, CPUC1 CPUT0, CPUC0 Name Reserved, set = 0 Reserved, set = 1 Reserved, set = 1 Reserved, set = 1 Reserved, set = 1 CPUT/C_ITP Output Enable 0 = Disabled (three-state), 1 = Enabled CPU(T/C)1 Output Enable, 0 = Disabled (three-state), 1 = Enabled CPU(T/C)0 Output Enable 0 = Disabled (three-state), 1 = Enabled Description
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CY28405
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved CPUT_ITP, CPUC_ITP CPUT1, CPUC1 CPUT0, CPUC0 Reserved Reserved Reserved Name Reserved, set = 0 Reserved, set = 0 CPUT/C_ITP Pwrdwn drive mode 0 = Driven in power- down, 1 = three-state CPU(T/C)1 Pwrdwn drive mode 0 = Driven in power-down, 1 = three-state CPU(T/C)0 Pwrdwn drive mode 0 = Driven in power-down, 1 = three-state Reserved Reserved Reserved Description
Byte 3: Control Register 3 Bit 7 @Pup 1 Name Description SW PCI_STP Function 0= PCI_STP assert, 1= PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume in a synchronous manner with no short pulses. Reserved PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Reserved PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled
6 5 4 3 2 1 0
1 1 1 1 1 1 1
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 1 1 1 Name USB_48 (404: 24_48MHz) USB_48 PCIF2 PCIF1 PCIF0 PCIF2 PCIF1 PCIF0 Description USB 48 (404: and 24MHz) Drive Strength Control 0 = High Drive Strength, 1 = Low Drive Strength USB_48 Output Enable 0 = Disabled, 1 = Enabled Allow control of PCIF2 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP Allow control of PCIF1 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP Allow control of PCIF0 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled PCIF0 Output Enable 0 = Disabled, 1 = Enabled
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CY28405
Byte 5: Control Register 5 Bit 7 6 5 @Pup 1 1 HW DOT_48 Reserved 3V66_3/VCH/SELVCH Name DOT_48 Output Enable 0 = Disabled, 1 = Enabled Reserved 3V66_3/VCH/SELVCH Frequency Select 0 = 3V66 mode, 1 = VCH (48MHz) mode May be written to override the power-up value. 3V66_3/VCH/SELVCH Output Enable 0 = Disabled,1 = Enabled Reserved 3V66_2 Output Enable 0 = Disabled, 1 = Enabled 3V66_1 Output Enable 0 = Disabled, 1 = Enabled 3V66_0 Output Enable 0 = Disabled, 1 = Enabled Description
4 3 2 1 0
1 1 1 1 1
3V66_3/VCH/SELVCH Reserved 3V66_2 3V66_1 3V66_0
Byte 6: Control Register 6 Bit 7 @Pup 0 Name REF PCIF PCI 3V66 3V66_3/VCH/SELVCH USB_48 DOT_48 CPUT, CPUT_ITP CPUC,CPUC_ITP Reserved Reserved Test Clock Mode 0 = Disabled, 1 = Enabled When Test Clock Mode is enabled, the FS_A/REF_0 pin reverts to a dedicated FS_A input, allowing asynchronous selection between Hi-Z and REF/N mode. Description
6 5
0 0
Reserved, Set = 0 Reserved, Set = 0 FS_A & FS_B Operation 0 = Normal, 1 = Test mode Reserved, Set = 0 Reserved, Set = 0 Spread Spectrum Enable 0 = Spread Off, 1 = Spread On
4 3 2
0 0 0
Reserved Reserved PCIF PCI 3V66 CPUT,CPUT_ITP CPUC,CPUC_ITP REF_1 REF_0
1 0
1 1
REF_1 Output Enable 0 = Disabled, 1 = Enabled REF_0 Output Enable 0 = Disabled, 1 = Enabled
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 @Pup 0 1 0 0 1 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Description
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CY28405
Byte 7: Vendor ID Bit 0 @Pup 0 Name Vendor ID Bit 0 Description
Byte 8: Control Register 8 Bit 7 6 5 @Pup 0 1 1 CPU PCIF PCI 3V66 Name Description Spread Spectrum Selection `000' = 0.20% triangular `001' = + 0.12, - 0.62% `010' = + 0.25, - 0.75% `011' = -0.05, - 0.45% triangular `100' = 0.25% `101' = + 0.00, - 0.50% `110' = 0.5% `111' = 0.38% SW Frequency selection bits. See Table 1.
4 3 2 1 0
0 0 0 0 0
FSEL_4 FSEL_3 FSEL_2 FSEL_1 FSEL_0
Byte 9: Control Register 9 Bit 7 6 5 4 3 2 @Pup 0 0 0 1 1 (`404: 1) 1 PCIF PCI 3V66 REF Reserved Reserved (Reserved for CY28404: REF2 Reserved Reserved Name Description PCIF Clock Output Drive Strength Control 0 = Low Drive strength, 1 = High Drive strength PCI Clock Output Drive Strength 0 = Low Drive strength, 1 = High Drive strength 3V66 Clock Output Drive Strength 0 = Low Drive strength, 1 = High Drive strength REF Clock Output Drive Strength 0 = Low Drive strength, 1 = High Drive strength Reserved Reserved (Reserved for CY28404: REF2 Output Enable 0 = Disabled, 1 = Enabled) Vendor Test Mode (always program to 0) PLL Bypass Test Vendor Test Mode (always program to 0) PLL Leakage Test
1 0
0 0
Byte 10: Control Register 10 Bit 7 6 @Pup 0 0 Name PCI_Skew1 PCI_Skew0 PCI skew control 00 = Normal 01 = -500 ps 10 = Reserved 11 = +500 ps 3V66 skew control 00 = Normal 01 = -150 ps 10 = +150 ps 11 = +300 ps Reserved, Set = 1 Reserved, Set = 1 Description
5 4
0 0
3V66_Skew1 3V66_Skew0
3 2
1 1
Reserved Reserved
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CY28405
Byte 10: Control Register 10 (continued) Bit 1 0 @Pup 1 1 Reserved Reserved Name Reserved, Set = 1 Reserved, Set = 1 Description
Byte 11: Control Register 11 Bit 7 6 @Pup 0 0 Reserved Recovery_Frequency Name Description Vendor Test Mode (always program to 0) This bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: Use Hardware settings 1: Use Last SW table Programmed values To enable this function the register bit must first be set to "0" before toggling to "1". 0: Do not reload 1: Reset timer but continue to count. This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD_TIMER time stamp Watchdog timer time stamp selection: 0000: Off 0001: 2 second 0010: 4 seconds 0011: 6 seconds . . . 1110: 28seconds 1111: 30seconds
5
0
Watchdog Time Stamp Reload
4 3 2 1 0
0 0 0 0 0
WD_Alarm WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0
Byte 12: Control Register 12 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CPU_FSEL_N8 CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used.
Byte 13: Control Register 13 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CPU_FSEL_N0 CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0 Description If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used.
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CY28405
Byte 14: Control Register 14 Bit 7 @Pup 0 FS_(E:A) Name Description FS_Override 0 = Select operating frequency by FS(E:A) input pins 1 = Select operating frequency by FSEL(4:0) settings Reserved, Set = 1 Reserved, Set = 0 Reserved, Set = 0 Reserved, Set = 0 Reserved, Set = 0 Reserved, Set = 0 Programmable output frequencies enabled 0 = Disabled, 1 = Enabled
6 5 4 3 2 1 0
1 0 0 0 0 0 0
Reserved Reserved Reserved Reserved Reserved Reserved Pro_Freq_EN
Dial-a-Frequency Programming
When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * N/M "N" and "M" are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. "G" stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A] or SEL[4:0]. The value is listed in Table 1. The ratio of N and M need to be greater than "1" [N/M> 1]. The following table lists set of N and M values for different frequency output ranges. This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Table 5. Examples of N and M Value for Different CPU Frequency Range Fixed Value for M-Value Register 48 48 48 Range of N-Value Register for Different CPU Frequency 200 - 250 189 - 249 167 - 200
Crystal Recommendations
The CY28405 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28405 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Frequency Ranges 100 -125
Gear Constants 24004009.32
126 - 166 32005345.76 167 - 200 48008018.65
Table 6. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm
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CY28405
As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitative loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Figure 1. Crystal Capacitive Clarification Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe 1
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Clock Chip
=
1 ( Ce1 + Cs1 + Ci1 +
1 Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal ..................................... using standard value trim capacitors Ce..................................................... External trim capacitors Cs ............................................. Stray capacitance (trace,etc) Ci ............. Internal capacitance (lead frame, bond wires etc) PD# (Power-down) Clarification
Ci1
Ci2 Pin 3 to 6p
The PD# pin is used to shut off all clocks and PLLs without having to remove power from the device. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the power down state. PD# - Assertion
Cs1
X1
X2
Cs2 Trace 2.8pF
XTAL Ce1
Ce2
Trim 33pF
Figure 2. Crystal Loading Example
PWRDWN# CPUT, 133MHz CPUC, 133MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818
When PD# is sampled LOW by two consecutive rising edges of the CPUC clock then all clock outputs (except CPUT) clocks must be held LOW on their next HIGH to LOW transition. CPU clocks must be held with CPUT clock pin driven HIGH with a value of 2x Iref and CPUC undriven as the default condition. There exists an I2C bit that allows for the CPUT/C outputs to be three-stated during power-down. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete
Figure 3. Power-down Assertion Timing Waveforms
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CY28405
PD# Deassertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 1.8 ms. The CPUT/C outputs must be driven to greater than 200 mV is less than 300 s.
Tstable <1.8ms
PWRDWN# CPUT, 133MHz CPUC, 133MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818
Tdrive_PWRDN# <300 s, >200mV
Figure 4. Power-down Deassertion Timing Waveforms
FS_A, FS_B VTT_PWRGD# PWRGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
Wait for VTT_PWRGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PWRGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 5. VTT_PWRGD Timing Diagram
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CY28405
S1 S2 VTT_PWRGD# = Low
Delay >0.25mS
VDDA = 2.0V
Sample Inputs straps
Wait for 1.146ms S0 S3 VDDA = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 6. Clock Generator Power-up/Run State Diagram
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CY28405
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non-functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 15 45 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD, VDDA VILI2C VIHI2C VIL VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD IPD Description 3.3 Operating Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current At 200 MHz and all outputs loaded per Table 9 and Figure 7 PD# Asserted Except Pull-ups or Pull-downs 0 < VIN < VDD IOL = 1 mA IOH = -1 mA Conditions 3.3V 5% SDATA, SCLK SDATA, SCLK Min. 3.135 - 2.2 VSS - 0.5 2.0 -5 - 2.4 -10 2 3 - 0.7VDD 0 - - Max. 3.465 - - 0.8 VDD + 0.5 5 0.4 - 10 5 6 7 VDD 0.3VDD 280 1 Unit V 1.0 - V V A V V A pF pF nH V V mA mA
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CY28405
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Conditions The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When Xin is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1 s duration Over 150ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/ (TR + TF) 45 9.9970 7.4978 4.9985 - - 175 - - - Math average, see Figure 7 Math average,see Figure 7 660 -150 250 - -0.3 See Figure 7. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V - 45 14.9955 14.9955 4.9500 4.5500 0.5 - - 45 29.9910 29.9910 12.0 Min. Max. Unit
47.5
52.5
%
TPERIOD T R / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIOD TSKEW TCCJ T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB 3V66 TDC TPERIOD TPERIOD THIGH TLOW T R / TF TSKEW TCCJ PCI/PCIF TDC TPERIOD TPERIOD THIGH
XIN period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period Any CPU to CPU Clock Skew CPU Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage 3V66 Duty Cycle Spread Disabled 3V66 Period Spread Enabled 3V66 Period 3V66 High Time 3V66 Low Time 3V66 Rise and Fall Times Any 3V66 to Any 3V66 Clock Skew 3V66 Cycle to Cycle Jitter PCIF and PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Enabled PCIF/PCI Period PCIF and PCI High Time
69.841 - -
71.0 10.0 500 300 55 10.003 7.5023 5.0015 100 125 700 20 125 125 850 - 550 VHIGH+0.3 - 0.2 55 15.0045 15.0799 - - 2.0 250 250 55 30.0009 30.1598 -
ns ns ps ppm % ns ns ns ps ps ps % ps ps mv mv mv V V V % ns ns ns ns ns ps ps % ns ns ns
Rev 1.0, November 20, 2006
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CY28405
AC Electrical Specifications (continued)
Parameter TLOW T R / TF TSKEW TCCJ DOT TDC TPERIOD THIGH TLOW T R / TF TCCJ USB TDC TPERIOD THIGH TLOW T R / TF TCCJ REF TDC TPERIOD T R / TF TCCJ Description PCIF and PCI Low Time PCIF and PCI Rise and Fall Times Any PCI Clock to Any PCI Clock Skew PCIF and PCI Cycle to Cycle Jitter Duty Cycle Period DOT High Time DOT Low Time Rise and Fall Times Cycle to Cycle Jitter Duty Cycle Period USB High Time USB Low Time Rise and Fall Times Cycle to Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Conditions Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V 10- s period Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V 125- s period Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Min. 12.0 0.5 - - 45 20.8257 8.994 8.794 0.5 - 45 20.8257 8.094 7.694 1.0 - 45 69.827 1.0 - - 10.0 0 Max. - 2.0 500 250 55 20.8340 10.486 10.386 1.0 350 55 20.8340 10.036 9.836 2.0 350 55 69.855 4.0 1000 1.5 - - Unit ns ns ps ps % ns ns ns ns ps % ns ns ns ns ps % ns V/ns ps ms ns ns
ENABLE/DISABLE and SET-UP TSTABLE All Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
Table 7. Group Timing Relationship and Tolerances Offset Group 3V66 to PCI Table 8. USB to DOT Phase Offset Parameter DOT Skew USB Skew VCH SKew Typical 0 180 0 Value 0.0 ns 0.0 ns 0.0 ns Tolerance 1000 ps 1000 ps 1000 ps Conditions 3V66 Leads PCI Min. 1.5 ns Max. 3.5 ns
Rev 1.0, November 20, 2006
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CY28405
Table 9. Maximum Lumped Capacitive Output Loads Clock PCI Clocks 3V66 Clocks USB Clock DOT Clock REF Clock Max Load 30 30 20 10 30 Units pF pF pF pF pF
Test and Measurement Set-up
For Differential CPU and SRC Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CPUT
TPCB
M e a s u re m e n t P o in t
2pF
CPUC IR E F
TPCB
M e a s u re m e n t P o in t
2pF
Figure 7. 0.7V Load Configuration
O u tp u t u n d e r T e s t P ro b e
Load Cap
3 .3 V s ig n a l s
tD C
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
Tr
Tf
Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameter Measurement) Table 10.CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Reference R, IREF - VDD (3*RREF) RREF = 475 1%, IREF = 2.32 mA Output Current IOH = 6*IREF VOH @ Z 0.7V @ 50
Rev 1.0, November 20, 2006
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CY28405
Ordering Information
Part Number CY28405OC CY28405OCT Lead Free CY28405OXC CY28405OXCT 48-pin Shrunk Small Outline package (SSOP) 48-pin Shrunk Small Outline package (SSOP) - Tape and Reel Commercial, 0 to 70 C Commercial, 0 to 70 C Package Type 48-pin Shrunk Small Outline package (SSOP) 48-pin Shrunk Small Outline package (SSOP) - Tape and Reel Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C
Package Drawing and Dimensions
48-Lead Shrunk Small Outline Package O48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 18 of 18

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